This course is devoted to the fundamental knowledge of testing Very Large-Scale Integrated circuits (VLSI). The emphasis is on the investigation of various technically feasible test solutions combining both Design-for-Testability hardware and Computer-Aided Design algorithms for test-pattern generation to make sure the overall testability and quality of manufactured ICs. It begins with the topics of fault modeling and fault simulation, followed by the algorithms of Automatic Test Pattern Generation (ATPG). Then, widely adopted Design-for-Testability (DFT) techniques in IC design industry, such as Scan Test, Built-In Self-Test (BIST), Test Compression, and IEEE-1149.1 Boundary Scan Test Standard will be elaborated. At the final stage, some selective advanced topics such as power & clock networks testing and logic fault diagnosis will also be discussed. Upon the completion of this course, the students will know how to apply all kinds of test solutions to make an IC easily testable and reliable in a cost-effective way.

1. Introduction
2. Fault Modeling
3. Fault Simulation
4. Design-for-Testability (DFT) and Scan Test
5. Automatic Test Pattern Generation (ATPG)
6. Delay Test
7. Built-In Self-Test (BIST)
8. Test Compression
9. Boundary Scan Test
10. Testing Clock and Power Network
11. Fault Diagnosis
12. Scan Chain Diagnosis using Artificial Neural Network

A1:    Review of Digital Circuit Design Methodology

A2:    Quick-and-Cool Scan Test Methodology

A3:    Optimization by Branch-and-Bound