This course is devoted to the fundamental knowledge of testing Very Large-Scale Integrated circuits (VLSI). The emphasis is on the investigation of various technically feasible test solutions combining both Design-for-Testability hardware and Computer-Aided Design algorithms for test-pattern generation to make sure the overall testability and quality of manufactured ICs. It begins with the topics of fault modeling and fault simulation, followed by the algorithms of Automatic Test Pattern Generation (ATPG). Then, widely adopted Design-for-Testability (DFT) techniques in IC design industry, such as Scan Test, Built-In Self-Test (BIST), and test compression will be introduced. Upon the completion of this course, the students will know how to apply all kinds of test solutions to make an IC easily testable and reliable in a cost-effective way.