邏輯設計Logic Design
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老師: 黃錫瑜
助教: 王逸生, 温景怡, 賴 淇
基本資訊
課程代碼
11110EECS101001
課程名稱
邏輯設計Logic Design
學分
3
學期
1111
單位
電資院 (EECS)
班級
一年級
修課人數
110 人
老師
助教
課程說明
課程簡介

 This course teaches the fundamental knowledge of designing a digital system. We will begin by introducing the number systems, Boolean algebra, and the logic gates. After that, we will discuss the simplification techniques for Boolean functions using Karnaugh Map as well as algorithmic procedures. In the second half, we will focus on the design techniques for combinational, sequential, and memory circuits. Finally, we will introduce the more modern design concept using Register-Transfer-Level (RTL) descriptions. Upon completion, the students will know how to realize a given digital system, e.g., a computer's arithmetic logic unit (ALU), into a logic circuit.

課程大綱
  1. Binary Systems                                    
  2. Boolean Algebra and Logic Gates                                                             
  3. Gate-Level Minimization                                                                                 
  4. Combinational Logic       
  5. Synchronous Sequential Logic                                                                  
  6. Register and Counters                                                                                       
  7. Memory and Programmable Logic                                                    
  8. Register-Transfer-Level (RTL) Logic Design
教科書
M. Mano and M. Ciletti, “Digital Design,” 4th edition or later, Pearson / Prentice Hall, 2019.
成績說明
Attendance 5%
Homeworks 32%
Midterm Exam. 30%
Final Exam. 33%
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